The invention relates to an IC with built-in self-test and a design method thereof, and in particular to an IC with built-in self-test and a design method thereof employed in a sigma-delta analog-to-digital converter (SD-ADC), degrading difficulty in designing the circuit and preventing performance degradation of the circuit caused by thermal noise.
Analog/mixed-signal testing requires a signal source generator and an analog response analyzer, which can be realized by many analog instruments/meters or by a mixed-signal automatic testing equipment externally. The testing always suffers from the I/O signal degradation or the noise effects on the analog stimulus and measurement. Any attempt to realize an on-chip analog/mixed-signal testing requires characterization and quantification of the signal source generator and the analog response analyzer first, which could be prohibitively expensive. The cost to test the analog portion of a mixed-signal device can be as high as 50% of the total cost.
Over sampling analog-to-digital and digital-to analog converters (ADC and DAC) have become popular for high-resolution medium-to-low-speed applications. The use of shaped quantization noise applied to over sampling signals is commonly referred to as a sigma-delta (ΣΔ) modulation. The main advantage of the sigma-delta modulation is its higher resolution, but testing thereof requires better resolution than itself. This modulation can provide a deadlock problem in the on-chip analog testing.
A digital stimulus measurement technique (DSMT) has been suggested in the related art. See C. K. Ong, K. T. Chen, and L. C. Wang, “Self-testing Second-Order Delta-Sigma Modulator Using Digital Stimulus” In Proc. VLSI Test Symposium, pp. 237–46, April 2002 (hereafter referred to as “related art”). According to the prior art, the test stimulus is a digital bit-stream transformed from a sinusoid wave by a software modulator as shown in FIG. 1. FIG. 2 is a system block diagram of the delta-sigma modulator in FIG. 1. In testing mode, an analog input signal X2 is disconnected from the modulator (SD-ADC) 20 and the bit-stream Si2 amplitude is reduced to maintain stability of the modulator 20. The amplitude reduction is accomplished by a gain module 22 of a design-for-test (Dft) circuit 21 of which the gain is ¼. In the related art, reference voltages are selected by the bit-stream Si2. The selected reference voltage is reduced by the gain module 22 and is then used to test the modulator 20.
Since the modulator 20 is a switch-capacitor (SC) type, the Dft circuit 21 requires a small capacitor. The capacitor can cause thermal noise, reducing performance degradation of the modulator 20. The analysis of thermal noise is described below.
It is assumed that the maximum value of the capacitor is 10 p, the max peak-to-peak signal is 1, and the over sampling rate is 400. When the Dft circuit 21 is not applied in the modulator 20, the analysis of thermal noise is represented by the following formula:                     ⁢          NoisePower      =                        KT          C                =                                            1.38              ×                              10                                  -                  23                                            ×              300                                      2              ×                              10                                  -                  12                                                              =                      2.07            ⁢                                                  ⁢            nV                                    SNR    =                                        10            ⁢                          log              ⁡                              (                                  SignalPower                                      2.07                    ⁢                                                                                  ⁢                    n                                                  )                                              +                      10            ⁢                          log              ⁡                              (                OSR                )                                                    ≈                  103.7          ⁢                                          ⁢          dB                    =              17.3        ⁢                                  ⁢        bit            
When the Dft circuit 21 is applied in the modulator 20 and the minimum capacitance of the capacitor is 0.75 p, the analysis of thermal noise is represented by the following formula:       NoisePower    =          74.3      ⁢                          ⁢      nV            SNR    =                                        10            ⁢                          log              ⁡                              (                                  SignalPower                                      74.3                    ⁢                                                                                  ⁢                    n                                                  )                                              +                      10            ⁢                          log              ⁡                              (                OSR                )                                                    ≈                  99.4          ⁢                                          ⁢          dB                    =              16.5        ⁢                                  ⁢        bit                            wherein, SNR represents signal-to-noise ratio, k Boltzmann constant, T absolute temperature, and ORS over sampling rate.        
According to the above analysis, the Dft circuit 21 with the capacitor causes resolution degradation of the modulator 20.
When designing an analog integrated circuit, the circuit size and cost are limited, causing performance of internal components therein to be insufficient, thus capacitors are limited to a maximum value. Therefore, when maximum capacitance does not change, the Dft circuit 21 causes resolution degradation, that is, performance degradation. Moreover, the technique of the related art is limited to application in one specific circuit, thus, the technique suggested by the related art is not capable of utilizing various circuits correctly.